However, some machines appear to have this feature incorrectly setup. This is useful for the chipset where the base address of the linear framebuffer must be supplied by the user, or at depths 1 and 4bpp. Also for non PCI machines specifying this force the linear base address to be this value, reprogramming the video processor to suit. Author Write something about yourself. There is the limit of the maximum dotclock the video processor can handle, and there is another limitation of the available memory bandwidth. Options related to drivers can be present in the Screen, Device and Monitor sections and the Display subsections.

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However if you do try this option and are willing to debug it, I’d like to hear from you. Chips and Technologies driver. The correct options to start the server with these modes are.

Chips and Technologies PCI BUS drivers

Some users prefer to use clocks that are defined by their BIOS. However, 8 and 24 bit colour depths seem to work fine.

You can use the ” SetMClk ” option in your xorg. Using this option the user can override the maximum dot-clock and specify any value they prefer. Which results in the x mode only expanded to x The HiQV series of chips have three programmable clocks.

If you get techhologies error with this option try using the ” SetMClk ” option to slow the memory clock. The server will limit the maximum dotclock to a value as specified by the manufacturer. For this reason the default behaviour of the server is to use the panel timings already installed in the chip.


In its current form, X can not take advantage of this second display channel. Now the maximum memory clock is just the maximum supported by the video processor, not the maximum supported by the video memory.

This driver must be considered work in progress, and those users wanting stability are encouraged to use the older XFree86 3. Disabling hidden DRAM refresh may also help. Use caution with this option, as driving the video processor beyond its specifications might cause damage.

But assuming your memory clock is programmed to these maximum values the various maximum dot clocks for the chips are. The current programmable clock will be given as the last clock in the list. The following options are of particular interest to the Chips and Technologies driver.

Chips and Technologies drivers – Chips and Technologies Video Drivers

This document attempts to discuss the features of this driver, the options useful in configuring it and the known problems. Login or create an account to post a review.

The chipset has independent display channels, that can be configured to support independent refresh rates on the flat panel and on the CRT. Modeline “x 8bpp” This driver modifies the bypixel resolution to run at a lower vhips rate.


Sexually explicit or offensive language. The total memory requirements in this mode of operation is therefore similar to a 24bpp mode. Options related to drivers can be present in the Screen, Device and Monitor sections and the Display subsections.

Also the maximum size of the desktop with this option is x, as this is the largest window that the HiQV multimedia engine can display. The order of precedence is Display, Screen, Monitor, Device.

The exception technoloiges for depths of 1 or 4bpp where linear addressing is turned chipx by default.

It is enabled by default for machines since the blitter can not be used otherwise. For a complete discussion on the dot clock limitations, see the next section. We only work 6555 trusted advertising partners.

Information for Chips and Technologies Users

So with the ” Overlay ” option, using the ” SetMClk ” option to reduce the speed of the memory clock is recommended. There are therefore a wide variety of possible forms for all options.

At this point no testing has been done and it is entirely possible that the ” MMIO option will lockup your machine.